The present invention relates to analog integrated circuits, and particularly to integrated circuits which provide a selectable resistance value between two external terminals thereof.
Some Previous Integrated Circuits with Programmable Resistance
Xicor's X9MME part, which is believed to be prior art to the present application (at least in the form here described), is an "E.sup.2 POT.TM. Digitally Controlled Potentiometer." This part is described, in the Xicor literature, as "a solid state non-volatile potentiometer" which "is ideal for digitally controlled resistance trimming. The X9MME is a resistor array composed of 99 resistive elements. Between each element and at either end are tap points accessible to the wiper element. The position of the wiper element on the array is controlled by the CS*, U/D*, and INC* inputs. The position of the wiper can be stored in nonvolatile memory and is recalled upon a subsequent power-up." The U/D* (up/down) input "controls the direction of the wiper movement . . . ." The increment (INC*) input, when toggled, will "move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D* input."
Banezhad and Gregorian, "A Programmable Gain/Loss Circuit," 22 IEEE Journal of Solid-State Circuits 1082 (1987), shows a programmable circuit which can provide gain/loss values from -25.5 dB to +25.5 dB, in 0.1 dB increments. The individual gain/loss stages are apparently provided by op amp.sup.1 stages with resistive voltage dividers switched into the feedback connection (for gain) or into the output line (for loss). FNT .sup.1 "Op amps," or operational amplifiers, are voltage amplifiers with highly linear gain characteristics. They are used as building blocks in a wide variety of analog circuits.
U.S. Pat. No. 4,849,903 to Fletcher and Ross, entitled "Digitally controlled system for effecting and presenting a selected electrical resistance," purports to show
A digitally controlled resistance generator (10) in which resistors (16-38) having values selected according to an expression 2.sup.N-1 R, where N is equal to the number of terms in the expression, and R is equal to the lowest value of resistance, are electrically inserted into a resistive circuit in accordance with a parallel binary signal provided by an analog-to-digital converter (46) or a programmable computer (75). This binary signal is coupled via optical isolators (50-72) which, when activated by a logical "1," provides a negative potential to some or all of the gate inputs (96) of the normally "on" field effect transistors (98-120) which, when "on," shorts out the associated resistor. This applied negative potential turns the field effect transistors "off" and electrically inserts the resistor coupled between the source terminal (124) and the drain terminal (122) of that field effect transistor into the resistive circuit between the terminals (12, 14)..sup.2 FNT .sup.2 This patent also contains some interesting comments on the prior art, and on the motivation for a digital potentiometer, as follows: FNT "Other devices which may be used to generate a variable resistance include digitally controlled audio attenuators, two types of which are manufactured by National Semiconductor and DBX of New York. The National device can be incremented in 3 dB steps, which attenuates voltage or current by a factor 0.5, while the DBX device is capable of attenuating in 1 dB steps. Problems with these attenuators, however, are that even the smallest dB steps do not provide the resolution necessary to mimic a smoothly rising or falling resistance. Further, they cannot duplicate a linear resistive output because of logarithmic characteristics associated with attenuators. Still further, these attenuators exhibit distortions which may be tolerable at audio frequencies but which make them unsuitable to duplicate precise resistances, particularly below 100 ohms. FNT "In accordance with this invention, a resistance producing circuit is constructed wherein a digital data source provides digitally encoded binary bits. Each discrete bit is applied to a control input of one of a plurality of switching devices, each device having a pair of terminals which are switched responsive to the discrete bit. These switching devices are serially coupled by their pairs of terminals, and each switching device further has a resistor coupled between these switched terminals. These resistors are selectively electrically removed or included in a summing circuit responsive to the discrete bits to generate a resistive output which is linear with respect to the sequence of digitally encoded bits."
Innovative Digital Potentiometer Architecture
The presently preferred embodiment provides multiple features of novelty. To help provide a clear explanation of the claimed inventive features, some notable features of the preferred best mode of using the invention will first be described, before analyzing the particular points of innovation. However, it should be noted that this best-mode embodiment is necessarily somewhat specific, and does not define the full scope of the claimed inventive concepts.
The preferred best mode embodiment is an integrated circuit which provides two solid-state potentiometers. Each potentiometer contains a resistor string, and the endpoints of this resistor string are brought directly out to pins. For each potentiometer circuit, a "wiper" contact is also brought out to a pin.
Control logic receives a programmed resistance value, and accordingly activates one of 256 MOS switches (in each of the two potentiometers) to ohmically connect the wiper contact to a selectable intermediate point in the resistor string.
Thus, the user sees two three-terminal potentiometers, which can be used in essentially the same circuit configurations as two discrete mechanically-operated potentiometers could be, and which have the added advantage of being easily programmable by digital commands over a serial bus.
A multiplexed wiper port is also brought out. This permits the user to use the two potentiometers of each chip as one, as described below.
The resistor string is electrically floating if the external terminals are unconnected. Thus, the user really does have a well-behaved passive resistor to make use of. A passive resistor can be emulated with switched capacitors, or with active devices, but the noise and nonlinearity characteristics will typically not be as good as those of a simple passive device. Moreover, the temperature dependence will be different, which may be significant in some applications.
In the presently preferred embodiment, a connection is provided for a substrate bias connection. In a system where negative voltages are present, this bias connection can be connected to a negative voltage (as low as -5.5 V, in the presently preferred embodiment). If this is done, then voltages as negative as the bias voltage can be applied to the resistor string with no ill effects.
An alternative would be to use charge pumping techniques to avoid any problems of latchup. (This is done in the Xicor part referenced above.) However, such charge pumping techniques will tend to introduce electrical noise, which is very undesirable in an analog system.
Note that the potentiometer configuration is particularly convenient in analog circuits, since a single potentiometer can be used to configure the two resistors which define an op amp's gain.
Serial Control Interface
The selected resistor value is received over a simple serial port configuration. While the RST* line is held high, each pulse on the CLK (clock) line will cause a new bit of data to be shifted into a shift register. When the RST* line goes low, the value in the shift register is immediately applied to change the resistance at the wiper.
A similar serial command interface, and the daisy chain, were in the DS1292 Eliminator..sup.3 See U.S. Pat. No. 4,850,000, which is hereby incorporated by reference. FNT .sup.3 This chip, and its data sheet in the 1989 Dallas Semiconductor Databook, are available from Dallas Semiconductor Corp., 4350 South Beltwood Parkway, Dallas 75244, and are hereby incorporated by reference.
Daisy-Chaining to Control Multiple Chips
In the presently preferred embodiment, each chip has not only clock, reset, and data inputs, but also has a data output. As data is clocked into the data input pin, and shifted through the shift register, the data at the other end of the shift register is connected (through an output buffer) to drive a data output pin.
Combination with Nonvolatized Serial Memory
A particularly attractive configuration is to combine a nonvolatized serial memory on the serial control bus, such as a DS1204. The DS1204 (or equivalent) stores the desired resistor settings during periods when system power is off. At power-up, the system controller simply commands a read from the DS1204, and clocks the serial bus the needed number of times to reload the desired resistor settings into the potentiometer chips.
The data in the serial memory is preferably organized so that the last 17 n bits of readout will contain the desired values to set into n potentiometer chips. Thus, the serial memory can share a common serial bus with the potentiometer chips; the protocol bits which are initially supplied to the serial memory will simply be shifted on through the potentiometers, and will not affect the final value of their settings.
Directly Writable Arbitrary Value
A significant advantage of the disclosed architecture is that the resistance value is directly selectable: there is only one step from position 1 to (for example) position 128. By contrast, the increment/decrement architecture of the Xicor part slows response and may provide unwanted intermediate states.
Synchronized Update
A further advantage of the disclosed architecture is that the change in resistance value occurs when the RST* line changes state. Thus, the timing of a change can be controlled independently of the particular change sought. Moreover, when multiple chips are daisy-chained onto a common serial command bus (as described below), all of the chips will change state at the same time.
Chip with Multiple Digitally-Controlled Potentiometers which are Stackable or Separable
In the presently preferred embodiment, the two pots on chip each have 256 bits of resolution, but can be stacked to achieve a single pot with 512 bits of resolution.
This can be performed very simply, by connecting the end terminals of the two potentiometers in series. (That is, the "high" pin H0 of one pot is tied to the "low" pin L1 of the other pot, and the remaining two high/low pins H1 and L0 provide the end terminals for the merged pot.) The user does not have to provide logic to select between the wiper pins W0 and W1: The wiper output for the merged pot is provided by a separate output pin ("S.sub.OUT "), and an additional most-significant selection bit controls a low-impedance gate which connects this to one of the two wiper terminals W1 and W0.
Innovative Thin-Film Resistor Structure
In the preferred layout, the contacts land on tabs which extend out from the resistor string, and do not land directly on the resistor string itself. There are several resulting advantages: One advantage is that variations in contact lithography and contact edge do not affect the long-range resistance of the resistor itself.
Moreover, the lack of "dogbone" shapes in the resistor string makes it easier to compute the resistance value of the string.
A further advantage of this layout technique is that the overall scale of the variable resistance can easily be changed simply by changing the width of the polysilicon in the meandering line which provides the resistor.
Note that, in the resistor meander, it is not necessary for the individual stages to be equal. For example, if the two arrays are given different increment values, a "double wiper" architecture could be used to map the most significant bits onto one side of the array, and less significant bits onto the other side of the array, so that the desired total resistance would be seen between the two wipers.
Note that the resistor array could be designed, for example, to have a logarithmic scale. This may be useful in telecomm applications, such as .mu.-law scaling or analogous scaling algorithms.
Innovative Architecture for Digitally-Controlled Complex Impedances
The disclosed architecture also can be adapted to provide a digital capacitor integrated circuit. The electrical configuration used for the capacitors is significantly different from that used for variable resistance, since capacitors are added by connecting them in parallel.
Scaling Capacitors in Powers of Two
In the presently preferred version of this embodiment, the selectable capacitor units have capacitances which are scaled in powers of two. This simplifies the switching logic, since fewer switches are needed. Moreover, since the capacitor values are scaled in powers of two, no decoder is needed: the 8 bits from the command register can be directly connected to select some combination of the 8 binary-scaled capacitors.
To make this scaling precise, without problems due to fringing fields, the higher-value capacitors are constructed by wiring multiple identical capacitors in parallel.
Maximum Total Capacitance
In the layout of FIG. 7, the total area of the cells (for one potentiometer unit) is approximately 20 mils by 110 mils. (This gives an area of 2200 square mils, or 1.23 mm.sup.2.) Using MOS capacitors to ground, with a typical specific capacitance of 1.5 fF per micron.sup.2, this layout provides a maximum total capacitance of about 1000 pF. However, only about 10% of the cell area is used for the actual resistor line, and, if only this much area were used for capacitors, the maximum total capacitance would be only about 100 pF, which is too small for many applications. Therefore, it is preferable to expand the area used for capacitors, in this embodiment. Of course, the layout sizes can readily be scaled, but this gives an idea of the capacitance magnitudes which are readily available.
Capacitor Device Structure
In the presently preferred embodiment, the capacitors are MOS capacitors to ground. FIG. 10 shows a sample embodiment which includes a variable capacitance, selected by bits loaded in over a serial interface.
A contemplated alternative embodiment uses poly-to-poly capacitors. Such capacitors have the advantage of greater linearity than MOS capacitors to bulk silicon. In the contemplated best mode, it is anticipated that poly-to-poly capacitors, with an oxide-nitride-oxide dielectric, would be used for the capacitive elements, to help achieve a high and reproducible specific capacitance per unit area. See U.S. Pat. No. 4,613,956, which is hereby incorporated by reference. Of course, other capacitor technologies, such as a corrugated trench capacitor, could also be used instead.
In a further alternative, if poly-to-poly capacitors are used, the capacitor could be configured to be floating between two external terminals. However, in this case, ESD protection structures would have to be added.
Alternative Three-Terminal Capacitor Architecture
An alternative configuration uses an architecture which is more closely analogous to that of the potentiometer of FIG. 1:
256(or 2.sup.n) cells each include a capacitor to ground, with an upper plate linked the RESIN terminal;
each cell also includes a decoder, buffer, and transmission gate, analogous to that shown in FIG. 8; however, one pair of connections is reversed, so that the transmission gates of all unselected cells are on, and the selected cell's transmission gate is off;
each cell's transmission gate is connected to link the RESIN terminal to the RESOUT terminal.
This alternative has the advantage that two complementary variable capacitances are available, at the two external terminals. This may be advantageous for applications where a ratio of two capacitors needs to be dynamically adjusted (e.g. for dynamic signal filtering with an averaging capacitor).
Combination of Analog Functions
A great deal of work has been directed to emulating analog filter functions in digital or switched-capacitor circuits. However, an advantage of the architecture described here is that it really does provide an analog element: the only switching is DC switching, to connect or disconnect additional elements. Thus, the disclosed architecture may be applicable to trimming, matching, and tuning applications in circuits operating at VHF frequencies or higher.
The disclosed architecture provides analog functions which are readily programmable by a simple serial interface. One of the key advantages of digital signal processing has been the ability to rapidly change a filter function, and the disclosed architecture provides a much simpler way to do this. Such programmable analog functions can also be used to provide front-end processing of a signal source, in combination with digital signal processors.
In fact, a chip embodiment which is believed to be particularly advantageous is a chip which has one potentiometer and one variable capacitor on the same chip. This can be used, in combination with simple analog gain stages, to configure a variety of circuits which provide desired frequency-domain or time-domain characteristics.
Complex functions can be implemented by combining a digitally-controlled capacitor with a digitally-controlled resistor and an analog gain stage, in accordance with the teachings set forth herein. Such combinations can provide a variety of complex functions. For example, this can be used to provide a programmable bandpass filter, whose center frequency and Q are both tunable. The disclosed innovations permit complex analog functions to be readily implemented. The closed-loop gain of an amplifier gain stage is normally adjusted using a resistor ratio..sup.4 However, some embodiments of the disclosed architecture permit both the center frequency and Q of a gain stage to be selected independently. A programmable potentiometer, as described above, is linked to a gain stage, to define the gain of an op amp. In addition, a switchable network of capacitors is used to define the reactance which will determine the center frequency of the stage. The flexible filter design options thus provided can be used by system designers for programmable gain/attenuation, programmable analog phase-shifting, or other functions. FNT .sup.4 When a feedback resistor R.sub.F is interposed in the feedback path from the output terminal to the negative input terminal of a differential amplifier, and an input resistance R.sub.in is interposed between the negative input terminal signal and an incoming signal V.sub.in, the voltage gain V.sub.out /V.sub.in will be equal to the ratio of the resistances -R.sub.F /R.sub.in.